1. Field of the Invention
The present invention relates to a method for checking a designing apparatus, and more specifically to the technology of making a check using FSM coverage measurement.
2. Description of the Prior Art
Recently, a digital circuit design described in an HDL (hardware description language), etc. fully using an EDA (electronic design automation) tool is performed. In the design, unlike the conventional designing method, hardware designing is performed concurrently with the development of software so that the processes performed by software such as data processing, protocol processing, etc. can be realized by a digital circuit in many cases. Therefore, when the system of a large-scale logical circuit is designed by an HDL, etc. there is a tendency that a debugging time during designing and a checking time required for shipping necessarily increases.
For example, a model of a logical circuit designed by the HDL description is generally checked for verification by inputting a verification suite (test bench) to a simulator. The progress of the verification is determined by checking whether or not the activation of a logical expression and a conditional statement described in the RTL (register transfer level) description, the coverage rate of each state, and the transition between states are covered (compensated for) by an existing verification suite. One of the checking processes is coverage measurement. The coverage measurement is an important item. Although a check is performed without understanding the quality of a test bench itself for use in the check, quantitative quality improvement cannot be directly attained. The coverage measurement (code execution coverage rate, branch execution coverage rate, pass execution coverage rate, MC/DC, etc.) quantitatively grasps how sufficiently a check has been made to objectively discriminate whether or not the shipping can be performed.
However, when a check is made by the coverage evaluation performed by measuring the coverage (scope of the compensation), there can be a case where the coverage rate does not reach 100%. A research to designate a cause by checking the description contents to attain the coverage rate of 100% takes much time, thereby increasing the debugging time during designing and the checking time for shipping.
According to Japanese Published Patent Application No. 2001-014365, the RTL description and the verification suite are input to the function test coverage measurement device for measuring the function test coverage and the RTL simplifying device for simplifying the RTL description in order to evaluate the coverage. Then, a converted verification suite is output. The output verification suite is generated by deleting an unnecessary portion relating to a redundant portion of the RTL description in the test vector included in the input verification suite. Using such a verification suite, the checking time can be successfully shortened.
As a method of improving the coverage measurement, there is a method proposed of first raising the coverage to a certain extent in a black box test (test in which a source code is not confirmed), then detecting a path or a code which has not been processed, generating a test case to process the portion, and conducting again the test.
Considering the coverage measurement of an FSM (finite state machine), there are FSM state coverage for measurement to determine whether or not a defined state has been detected by extracting the FSM in a module unit, and FSM arc coverage for measurement to determine whether or not a transition has occurred by a conditional branch from each state. FIG. 1 shows the FSM. The method is generally expressed by the state (state: Sx) and the transition (arc: Ax). In the state machine shown in FIG. 1, there are a condition which changes by the transition indicated by the arrow A0 and a condition which changes in the route indicated by the arrow A2 as the conditions for transition to the state S1 from the state S0, and the transition causes a further transition to the next state of S1.
Similarly, when the condition from S0 to S2 is satisfied, the transition is performed in the route of the transition of A1. The transition to S3 is also performed through the route of A3. When a transition is performed from S1 to S3, the route of A5 is used. In the case of S2, the transition is performed to S0 and S3 respectively through the routes A4 and A7. In the case of S3, the transition is performed to S2 through A6.
In the check, the states are covered if the transition is performed to all states using the four states from S0 to S3 as the total states. Similarly, when all transitions occur using eight transitions from A0 to A7 as the total transitions, the arcs are covered, thereby passing the check.
However, in the FSM state coverage, all defined as states (Sx) are included as a total number. Therefore, if an error state, etc. which causes no transition as a design intention is described, no transition occurs to the error state. Accordingly, the transition check result does not reach 100%. That is, when the total number of states (Sx) is set as a denominator and the number of actual transition states through a simulation, etc. is set as a numerator, the numerator is not equal to the denominator so far as there is a state that causes no transition. Therefore, the result is not 100%.
Furthermore, since the total number includes the transitions (Ax) optimized only in the module having the FSM description in the FSM arc coverage, the result of 100% is not attained when hierarchical levels of modules contain a constant description or an exclusive language description.
When the FSM coverage result does not reach 100% after performing a simulation, it is necessary to confirm whether or not there is a problem by extracting an uncovered portion and analyzing the cause. If the description includes no problem, an unnecessary cause analysis is performed, which is an inefficient operation.